The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method generally provide measures to achieve expedited central-alignment of data (DQ) and data strobe signals (DQS) one relative to the other. In such manner, high speed data transfers to and from error-prone nonvolatile memory such as flash devices may be performed with a reduced risk of data loss.
While various approaches to training random access memory (RAM) to effectively communicate in reliable manner at high speeds are known in the art, no suitable prior art approach presently exists for nonvolatile memory (NVM) systems that account for their unique characteristic restrictions. As electronic device speeds and component density in devices increase and as timing tolerances become smaller, the need for precise training and synchronization between data strobe and data signals in nonvolatile memory and their memory controllers are only exacerbated.
There is therefore a need for a system and method for reliable high speed data transfer with multiple data rate nonvolatile memory. There is a need for training and alignment of data and data strobe signals between memory controllers and corresponding nonvolatile memory. More particularly, there is a need for optimized and expedited alignment of timing signals between a double data rate (DDR) interface memory controller and nonvolatile memory devices.